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Integrated Circuit Systems, Inc.
ICS91730
Low EMI, Spread Modulating, Clock Generator
Features: * ICS91730 is a Spread Spectrum Clock targeted for Mobile PC and LCD panel applications that generates an EMI-optimized clock signal (EMI peak reduction of 7-14 dB on 3rd-19th harmonics) through use of Spread Spectrum techniques. * ICS91730 focuses on the lower input frequency range of 14.318 to 80.00 MHz with a spread modulation of 20kHz to 40kHz. Specifications: * Supply Voltages: VDD = 3.3V 0.3V * Frequency range: 14.318 MHz Fin 80 MHz * Cyc to Cyc jitter: <150ps * Output duty cycle 45-55% * Guarantees +85C operational condition. * 8-pin SOIC * Reference input
Pin Configuration
CLKIN VDD GND CLKOUT
1 2 3 4 8 7 6 5
PD#* SCLK SDATA REF_OUT/FS_IN1*
8 Pin SOIC * Internal Pull-Up Resistor
Functionality
FSIN_1 0 1 MHz 14.318 MHz in --> 27MHz out 27.00MHz in --> 27.00MHz out Spread % default -0.8 down spread -1.25 down spread
Block Diagram
REFOUT CLKIN PLL1 Spread Spectrum Spectrum CLKOUT CLKOUT
PD# SDA SDATA SCLK FS_IN1
Control Logic Config. Reg.
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ICS91730
Pin Descriptions
PIN # 1 2 3 4 5 6 7 8 PIN NAME CLKIN VDD GND CLKOUT REF_OUT/FS_IN1* SDATA SCLK PD#* PIN TYPE PWR IN OUT I/O I/O PWR PWR PWR DESCRIPTION Input for reference clock. Power supply, nominal 3.3V Ground pin. Modulated clock output. Un-modulated 3.3V reference clock output. Frequency select latch input. Refer to the functionality table. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. Asynchronous active low input pin, with 120Kohm internal pull-up resistor, used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
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ICS91730
Table 1: Frequency Configuration Table (See I2C Byte 0)
FS4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FS3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Sprd Type Sprd %
DOWN SPREAD (-) 0.60 0.80 1.00 1.25 1.50 2.00 0.50 1.00 0.60 1.00 0.80 0.3
14in/27out
CENTER SPD (+/-)
DOWN SPREAD (-) CTR SPD
14in/14out 27in/27out
DOWN SPREAD (-)
1.50 1.75 2.00 2.50 3.00 1.25 0.40 0.50 0.70 1.00 1.20 1.50 0.60 0.80 1.00 1.25 1.50 2.00 0.50 1.00
CENTER SPD (+/-)
48in/48out 66in/66out
DOWN SPREAD (-)
CENTER SPD (+/-)
Above is the hard coded 5 bit (32 entry) ROM table. FS3:0 are ONLY accessible through I2C software programming bits (byte0 bits5:7). FS4 can also be decoded from FS_IN1 latched input hardware pins. FS_IN1 FS4. Upon power-up the default is to use hardware selection of FS_IN1 latched value. FS3 = 0, FS2 = 0, FS1 = 0, FS0 = 1 upon power-up (refer to the functionality table on page 1). To access non-default spread entries in the ROM, byte0 programming should be used. In order to change the power up default of FS_IN1 = 1 (-1.25% down spread) to any other spread % entry, first change byte0bit 0 to software selection by switching this bit to a `1' and then program the desired percentage by changing byte0 bits 7:3.
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ICS91730
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D4 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D5 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D4(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D4(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D5(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
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Not acknowledge stoP bit
4
ICS91730
Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Pin # -
Bit 0 Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Affected Pin Name Control Function FS0 Spread/FS0 FS1 Spread/FS1 FS2 Spread/FS2 FS3 Spread/FS3 FS4 FS4 PD# Tri_Sate PD# Tri_Sate Spread Enable Spread Enable Spread Spectrum Control FS 3:4 Hard/Software HW/SW Control Select Affected Pin Name Control Function REF_OUT REF_OUT_Enable REF_OUT Slew Rate REF-OUT FS-IN_1 FS-IN_1 Readback (Reserved) (Reserved) CLK_OUT Slew Rate CLK-OUT CLK_OUT CLK_OUT_Enable (Reserved) (Reserved) (Reserved) (Reserved) Affected Pin Name Control Function (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Type RW RW RW RW RW RW RW
Bit Control 0 1 Srpead Pecentage See Table1 These are I2C bits only Hi-Z OFF LOW ON
PWD 1 0 0 0 0 1 1
RW
HW
SW
0
Pin # -
Type RW RW R R RW RW R R
Bit Control 0 1 Disable Enable Nominal Fast Nominal Fast Disable Enable Bit Control 0 1 Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable
PWD 1 1 X 0 1 1 1 1
Pin # x x x x x x x x
Type RW RW RW RW RW RW RW
PWD 1 1 1 1 1 1 1 1
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ICS91730
Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Affected Pin Pin # X X X X x X X X Name (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Control Function (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Type RW RW RW RW RW RW RW RW
Bit Control 0 1 PWD 1 1 1 1 1 1 1 1
Pin # X X X X X X X X
Affected Pin Name Control Function (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Affected Pin Name Control Function (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Type RW RW RW RW RW RW RW RW
Bit Control 0 1 Bit Control 0 1 -
PWD 1 1 1 1 1 1 1 1
Pin # X X X X X X X X
Type RW RW RW RW
PWD 1 1 1 1 1 1 1 1
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ICS91730
Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin # X X X X X X X X
Affected Pin Name Control Function Revision ID Bit 3 (Reserved) Revision ID Bit 2 (Reserved) Revision ID Bit 1 (Reserved) Revision ID Bit 0 (Reserved) Vendor ID Bit 3 (Reserved) Vendor ID Bit 2 (Reserved) Vendor ID Bit 1 (Reserved) (Reserved) Vendor ID Bit 0
Type R R R R R R R R
Bit Control 0 1 -
PWD 1 1 1 1 1 1 1 1
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ICS91730
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Voltage on any pin with respect to GND . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 3.7 V -0.5 to +3.7 V -55C to +150C 0.5 W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL VIN = VDD Input High Current IIH IIL1 VIN = 0 V; Inputs with no pull-up resistors Input Low Current Powerdown Current IDD3.3PD Fi VDD = 3.3 V Input Frequency Lpin Pin Inductance Logic Inputs CIN 1 COUT Output pin capacitance Input Capacitance X1 & X2 pins CINX 1 Transition time Ttrans To 1st crossing of target frequency 1 Ts From 1st crossing to 1% target frequency Settling time 1 TSTAB From VDD = 3.3 V to 1% target frequency Clk Stabilization 1 Delay tPZH,tPZL Output enable delay (all outputs)
1
MIN 2 VSS - 0.3 -5 -5
TYP
MAX VDD + 0.3 0.8 5 5 7 5 6 45 3 3 3 10
1 14.318
27
36
1
UNITS V V mA mA mA MHz nH pF pF pF ms ms ms ns
Guaranteed by design, not 100% tested in production.
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ICS91730
Electrical Characteristics - CLKOUT
TA = 0 - 85C; VDD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS IOH = -1 mA Output High Voltage VOH3 IOL = 1 mA Output Low Voltage VOL3 Rise Time tr3 VOL = 0.41V, VOH = 0.86V Fall Time tf3 VOH = 0.86V VOL = 0.41V measurement from differential wavefrom dt3 Duty Cycle 0.35V to +035V 1 tjcyc-cyc VT = 50% Jitter, Cycle to cycle
1
MIN 2.4 0.5 0.5 45
TYP
MAX 0.4 1 1 55 150
UNITS V ns ns % ps
0.6 0.6 50 50
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 85C; V DD = 3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP1 V OH1 V OL1 I OH1 IOL1 t r11 t f11 dt11 t jcyc-cyc
1 1
CONDITIONS VO = V DD*(0.5) IOH = -1 mA IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, V OL @MAX = 0.4 V VOL = 0.4 V, V OH = 2.4 V VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V VT = 1.5 V
MIN 20 2.4 -29 29 1 1 45
TYP 48
MAX UNITS 60 V 0.4 -23 27 V mA mA ns ns % ps
1.2 1.2 51 105
2 2 55 300
Guaranteed by design, not 100% tested in production.
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ICS91730
150 mil (Narrow Body) SOIC
SYMBOL A A1 B C D E e H h L N In Millimeters COMMON DIMENSIONS MIN MAX 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 SEE VARIATIONS 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 SEE VARIATIONS .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 SEE VARIATIONS 0 8
VARIATIONS N 8 D mm. MIN 4.80 MAX 5.00 D (inch) MIN MAX .1890 .1968
Reference Doc.: JEDEC Publication 95, MS-012
10-0030
8-pin SOIC
Ordering Information
ICS91730yMLF-T
Example:
ICS XXXX y M LF- T
Designation for tape and reel packaging RoHS Compliant (Optional) Package Type M = SOIC Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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ICS91730
Revision History
Rev. B C Issue Date Description 06/25/04 Add Lead Free package description to Ordering Information 06/29/04 Add Revision History table to datasheet. 1. Revise ABS Max Ratings. 2. Updated REF Electrical Characteristics Table. 05/23/05 3. Updated LF Ordering Information from "Lead Free" to "RoHS Compliant". Page # 10 11
D
8-10
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